1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a plurality of circuits to which a power source potential is supplied independently.
2. Description of Related Art
FIG. 1 is a schematic view showing a structure of a conventional semiconductor integrated circuit using a plurality of power sources. Although FIG. 1 shows the structure using two power source systems, the same structure applies to a circuit with three or more power source systems. In FIG. 1, numeral 1 indicates semiconductor device including an element group (will be referred to as a first power system element group hereinafter) 2, which is connected between a first power source V.sub.CC and a ground V.sub.SS1, and an element group (will be referred to as a second power system element group hereinafter) 3, which is connected between a second power source V.sub.DD and a ground V.sub.SS2. The first power system element group 2 includes a plurality of output interfaces 4a, 4b, 4c . . . , which output signals 5a, 5b, 5c . . . to input interfaces 6a, 6b, 6c . . . included in the second power system element group 3 respectively.
In some cases, the semiconductor integrated circuit using a plurality of power sources as described above may operate in such a manner that the power from one of the power sources is cut off while the element group connected to the other power source is operated. This operation is carried out, for example, in the following case. The second power system element group 3 is formed of volatile memories such as RAM, and the first power system element group 2 is formed of functions elements other than those of the second power system element group 3, such as a CPU, ROM, a timer and an A/D converter. Usually, the first power source V.sub.CC is turned off in order to achieve lower power consumption when carrying out the back-up for the purpose of holding data in the volatile memories. In this operation, since the second power system element group 3 (e.g., RAM) which is connected to the second power source V.sub.DD functions as if it operates correctly even while the first power source V.sub.CC is turned off. This operation is referred to as a RAM backup function. In practice, however, such a phenomenon may occur that, when turning off the first power source V.sub.CC, a through current flows through the second power system element group 3 (e.g., RAM), resulting in lowering of the potential of the second power source V.sub.DD. This phenomenon will be described below.
FIG. 2 is a circuit diagram showing a specific example particularly related to the output interface 4a and the input interface 6a shown in FIG. 1. A signal 7 sent from a internal circuit 2a of the first power system element group 2 shown in FIG. 1 is fed to the output interface 4a formed of an inverter circuit of a negative logic, and is supplied therefrom, as an output signal 5a inverted and amplified by the output interface 4a, to the input interface 6a formed of an inverter circuit. The output interface 4a (and input interface 6a) may be formed of circuitry as shown in FIG. 3. A p-channel FET (Field Effect Transistor) 41 (61) and an n-channel FET 42 (62) are connected in this order between the first power source V.sub.CC (second power source V.sub.DD) and the ground V.sub.SS1 (V.sub.SS2). The output signal 5a is outputted from the connection between the p-channel FET 41 and the n-channel FET 42 of the output interface 4a, and the p-channel FET 61 and the n-channel FET 62 of the input interface 6a receive the output signal 5a on their gates.
Now, a description will be made on an operation for a transitional period during which the first power source V.sub.CC is turned off or the level of the potential is lowered in the semiconductor integrated circuit having the structure shown in FIGS. 2 anti 3. FIG. 4 is a timing chart showing the change of each potential and current when the first power source V.sub.CC is turned off. Before turning off the first power source V.sub.CC, the signal 7 shown in FIG. 2 is "L". When the signal 7 is "L", the p-channel FET 41 shown in FIG. 3 is ON and the n-channel FET 42 is OFF. Thereby, the output signal a which substantially reflects the potential of the first power source V.sub.CC is "H". When the first power source V.sub.CC is turned off, the potential of the output signal 5a gradually changes from "H" into "L" in accordance with the lowering of the potential of the first power source V.sub.CC. The operation at this time is carried out very slowly as compared with the ordinary switching operation.
In the case where the output signal 5a of an intermediate potential formed during a lowering of the potential is supplied to the input interface 6a, the p-channel FET 61 and the n-channel FET 62 become conductive, so that a so-called through current flows. In addition, since the output signal 5a changes slowly as described above, a through current, which is larger than a through current in the ordinary switching operation, flows through the input interface 6a. Thereby, the potential of the second power source V.sub.DD temporarily lowers (instantaneous lowering). This phenomenon is caused also at the time of lowering of a potential other than the time of turning off of the first power source V.sub.CC.
In a conventional semiconductor integrated circuit in which a large through current flows when the first power source V.sub.CC is turned off or the potential lowers as described above, the semiconductor integrated circuit may malfunction due to the instantaneous lowering of the voltage of the second power source V.sub.DD. In order to prevent this disadvantage, it is required, for example, to provide a power source which is remarkably strengthened so that influence upon the output of the second power source V.sub.DD can be suppressed even though a large current (through current) flows to the second power system element group 3.
As a prior art in which a through current does not flow to the second power system element group 3, Japanese Patent Application Laid-Open No. 3-46268 (1991) has disclosed a CMOS input buffer circuit (input interface 6a). In the CMOS input buffer circuit, an n-channel transistor for control is connected in series to the first transistor (61) and the second transistor (62), a p-channel transistor for control is connected in parallel to the first transistor (61), and these transistors for control are turned off in the battery backup mode. Further, Japanese Patent Application Laid-Open No. 3-185921 (1991) describes a semiconductor integrated circuit, in which a delay circuit formed of a plurality of FETs is placed preceding the output part (output interface 4a) so as to prevent the first and second switching units from turning on simultaneously.